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ARD2
1.00 for Rev B. Hardware
Airbag Reference Demonstrator using MPC5604P
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00001 00017 #ifndef _ADC_H 00018 #define _ADC_H 00019 00020 /* 00021 ************************************************************** 00022 * Defines, Macros and Typedefs 00023 **************************************************************/ 00024 /*** Constant Macros ***/ 00025 /* Default Yes and No defines */ 00026 #ifndef TRUE 00027 #define TRUE (1u) 00028 #endif 00029 #ifndef CLEAR 00030 #define CLEAR (0u) 00031 #endif 00032 #ifndef BITS_IN_NIBBLE 00033 #define BITS_IN_NIBBLE (4u) 00034 #endif 00035 #ifndef BITS_IN_BYTE 00036 #define BITS_IN_BYTE (8u) 00037 #endif 00038 #ifndef BYTES_IN_16 00039 #define BYTES_IN_16 (2u) 00040 #endif 00041 #ifndef BYTES_IN_32 00042 #define BYTES_IN_32 (4u) 00043 #endif 00044 #ifndef BITS_IN_32 00045 #define BITS_IN_32 (32u) 00046 #endif 00047 #ifndef BITS_IN_16 00048 #define BITS_IN_16 (16u) 00049 #endif 00050 #ifndef BIT_DEFINITION 00051 #define BIT_DEFINITION 00052 #define BIT0 (1u << 0u) 00053 #define BIT1 (1u << 1u) 00054 #define BIT2 (1u << 2u) 00055 #define BIT3 (1u << 3u) 00056 #define BIT4 (1u << 4u) 00057 #define BIT5 (1u << 5u) 00058 #define BIT6 (1u << 6u) 00059 #define BIT7 (1u << 7u) 00060 #define BIT8 (1u << 8u) 00061 #define BIT9 (1u << 9u) 00062 #define BIT10 (1u << 10) 00063 #define BIT11 (1u << 11) 00064 #define BIT12 (1u << 12) 00065 #define BIT13 (1u << 13) 00066 #define BIT14 (1u << 14) 00067 #define BIT15 (1u << 15) 00068 #define BIT16 (1u << 16) 00069 #define BIT17 (1u << 17) 00070 #define BIT18 (1u << 18) 00071 #define BIT19 (1u << 19) 00072 #define BIT20 (1u << 20) 00073 #define BIT21 (1u << 21) 00074 #define BIT22 (1u << 22) 00075 #define BIT23 (1u << 23) 00076 #define BIT24 (1u << 24) 00077 #define BIT25 (1u << 25) 00078 #define BIT26 (1u << 26) 00079 #define BIT27 (1u << 27) 00080 #define BIT28 (1u << 28) 00081 #define BIT29 (1u << 29) 00082 #define BIT30 (1u << 30) 00083 #define BIT31 (1u << 31) 00084 #endif 00085 00086 /* Instances */ 00087 #define ADC_MODULE_0 (0x00u) 00088 #define ADC_MODULE_1 (0x01u) 00089 00090 /* Max and mins */ 00091 #define ADC_CH_MAX ADC_CH15 00092 #define ADC_NO_MODULES (0x02u) 00093 00094 /* HW Status */ 00095 #define ADC_ST_IDLE (0x00u) 00096 #define ADC_ST_POWER_DOWN (0x01u) 00097 #define ADC_ST_WAIT (0x02u) 00098 #define ADC_ST_SAMPLE (0x04u) 00099 #define ADC_ST_CONVERSION (0x06u) 00100 00101 /* HW ISR Masks */ 00102 #define ADC_ISR_EOCTU_MASK BIT4 00103 #define ADC_ISR_JEOC_MASK BIT3 00104 #define ADC_ISR_JECH_MASK BIT2 00105 #define ADC_ISR_EOC_MASK BIT1 00106 #define ADC_ISR_ECH_MASK BIT0 00107 00108 /* SW Status */ 00110 #define ADC_ERR_BAD_INSTANCE BIT0 00111 00112 #define ADC_ERR_INVALID_RESULT BIT1 00113 00114 #define ADC_ERR_INVALID_CH BIT2 00115 00116 #define ADC_ERR_ONGOING_CONV BIT3 00117 00118 /* ADCConfig_t Masks */ 00119 #define ADC_DATA_CAN_BE_OVERWRITTEN (0x80000000u) 00120 #define ADC_DATA_CANT_BE_OVERWRITTEN (0X00000000u) 00121 #define ADC_DATA_IS_ALIGNED_LEFT (0x40000000u) 00122 #define ADC_DATA_IS_ALIGNED_RIGHT (0x00000000u) 00123 #define ADC_IS_IN_SCAN_MODE (0x20000000u) 00124 #define ADC_IS_IN_ONE_SHOT_MODE (0x00000000u) 00125 #define ADC_CTU_IS_ON (0x10000000u) 00126 #define ADC_CTU_IS_OFF (0x00000000u) 00127 #define ADC_AUTOCLOCK_OFF_EN (0x08000000u) 00128 #define ADC_AUTOCLOCK_OFF_DIS (0x00000000u) 00129 00130 #define ADC_EO_CTU_CONV_ISR_EN (0x04000000u) 00131 #define ADC_EO_CTU_CONV_ISR_DIS (0x00000000u) 00132 #define ADC_EO_INJ_CHAN_CONV_ISR_EN (0x02000000u) 00133 #define ADC_EO_INJ_CHAN_CONV_ISR_DIS (0x00000000u) 00134 #define ADC_EO_INJ_CHAIN_CONV_ISR_EN (0x01000000u) 00135 #define ADC_EO_INJ_CHAIN_CONV_ISR_DIS (0x00000000u) 00136 #define ADC_EO_CHAN_CONV_ISR_EN (0x00800000u) 00137 #define ADC_EO_CHAN_CONV_ISR_DIS (0x00000000u) 00138 #define ADC_EO_CHAIN_CONV_ISR_EN (0x00400000u) 00139 #define ADC_EO_CHAIN_CONV_ISR_DIS (0x00000000u) 00140 #define ADC_DMA_CLEARED_ON_READ (0x00200000u) 00141 #define ADC_DMA_CLEARED_ON_ACK (0x00000000u) 00142 #define ADC_DMA_EN (0x00100000u) 00143 #define ADC_DMA_DIS (0x00000000u) 00144 #define ADC_IS_CLOCKING_FULL_SPEED (0x00080000u) 00145 #define ADC_IS_CLOCKING_HALF_SPEED (0x00000000u) 00146 #define ADC_PR_INPLATCH_SET (0x00008000u) 00147 #define ADC_PR_INPLATCH_CLEAR (0x00000000u) 00148 #define ADC_PR_LSB_ROUND_DOWN (0x00004000u) 00149 #define ADC_PR_LSB_ROUND_UP (0x00002000u) 00150 #define ADC_PR_LSB_NO_ROUNDING (0x00000000u) 00151 #define ADC_PR_INPCMP_1 (0x00000200u) 00152 #define ADC_PR_INPCMP_2 (0x00000400u) 00153 #define ADC_PR_INPCMP_3 (0x00000600u) 00154 00155 /* ADCChConfig_t Masks */ 00156 #define ADC_CH_ISR_EN (0x80000000u) 00157 #define ADC_CH_ISR_DIS (0x00000000u) 00158 #define ADC_CH_DMA_EN (0x40000000u) 00159 #define ADC_CH_DMA_DIS (0x00000000u) 00160 00161 /* ADCChConfig_t Presets for speed */ 00162 #define ADC_LOW_SPEED_CONFIG (ADC_PR_INPLATCH_SET | ADC_PR_INPCMP_3 | \ 00163 ADC_PR_INPSAMP(255u)) 00164 /*** Function Macros ***/ 00165 #ifndef N_ELEMENTS 00166 #define N_ELEMENTS(X) (sizeof(X)/sizeof(*(X))) 00167 #endif 00168 00169 /* ADCChConfig_t Macros */ 00170 #define ADC_PR_INPSAMP(XX) (XX << 16u) 00171 /*** Enums ***/ 00172 enum ADC_CHANNELS /* Note that Pictus only has 16 channels per instance */ 00173 { 00174 ADC_CH0 = 0u, ADC_CH1, ADC_CH2, ADC_CH3, ADC_CH4, ADC_CH5, ADC_CH6, ADC_CH7, 00175 ADC_CH8, ADC_CH9, ADC_CH10, ADC_CH11, ADC_CH12, ADC_CH13, ADC_CH14, ADC_CH15, 00176 ADC_CH16, ADC_CH17, ADC_CH18, ADC_CH19, ADC_CH20, ADC_CH21, ADC_CH22, 00177 ADC_CH23, ADC_CH24, ADC_CH25, ADC_CH26, ADC_CH27, ADC_CH28, ADC_CH29, 00178 ADC_CH30, ADC_CH31, ADC_CH32, ADC_CH33, ADC_CH34, ADC_CH35, ADC_CH36, 00179 ADC_CH37, ADC_CH38, ADC_CH39, ADC_CH40, ADC_CH41, ADC_CH42, ADC_CH43, 00180 ADC_CH44, ADC_CH45, ADC_CH46, ADC_CH47, ADC_CH48, ADC_CH49, ADC_CH50, 00181 ADC_CH51, ADC_CH52, ADC_CH53, ADC_CH54, ADC_CH55, ADC_CH56, ADC_CH57, 00182 ADC_CH58, ADC_CH59, ADC_CH60, ADC_CH61, ADC_CH62, ADC_CH63, ADC_CH64, 00183 ADC_CH65, ADC_CH66, ADC_CH67, ADC_CH68, ADC_CH69, ADC_CH70, ADC_CH71, 00184 ADC_CH72, ADC_CH73, ADC_CH74, ADC_CH75, ADC_CH76, ADC_CH77, ADC_CH78, 00185 ADC_CH79, ADC_CH80, ADC_CH81, ADC_CH82, ADC_CH83, ADC_CH84, ADC_CH85, 00186 ADC_CH86, ADC_CH87, ADC_CH88, ADC_CH89, ADC_CH90, ADC_CH91, ADC_CH92, 00187 ADC_CH93, ADC_CH94, ADC_CH95 00188 }; 00189 00190 /*** TypeDefs ***/ 00191 typedef volatile struct ADC_tag* ADC_t; 00192 00193 typedef union 00194 { 00195 struct 00196 { 00197 uint32_t OverWriteEn :1; 00198 uint32_t LeftAligned :1; 00199 uint32_t ScanModeEn :1; 00200 uint32_t CTUEn :1; 00201 uint32_t AutoClockEn :1; 00202 uint32_t EOCTUIsrEn :1; 00203 uint32_t JEOCIsrEn :1; 00204 uint32_t JEOCHIsrEn :1; 00205 uint32_t EOCIsrEn :1; 00206 uint32_t EOCHIsrEn :1; 00207 uint32_t DMAClrOnRead :1; 00208 uint32_t DMAEn :1; 00209 uint32_t ClkSel :1; 00210 uint32_t Reserved :3; 00211 uint32_t LatchPhaseDuration :1; 00212 uint32_t Reserved0 :1; 00213 uint32_t OffShiftConfig :2; 00214 uint32_t Reserved1 :1; 00215 uint32_t ComparisonPhaseDuration :2; 00216 uint32_t Reserved2 :1; 00217 uint32_t SamplingPhaseDuration :8; 00218 } P; 00219 struct 00220 { 00221 uint16_t Mixed; 00222 uint16_t CTR; 00223 } R; 00224 uint32_t W; 00225 } ADCConfig_t; 00226 00227 typedef union 00228 { 00229 struct 00230 { 00231 uint32_t ChIsrEn :1; /* Not functional */ 00232 uint32_t ChDMAEn :1; 00233 uint32_t Reserved2 :17; 00234 uint32_t DMACh: 4; 00235 uint32_t Instance :1; 00236 uint32_t Channel :8; 00237 } P; 00238 uint32_t W; 00239 } ADCChConfig_t; 00240 00241 /* 00242 ************************************************************** 00243 * Declarations 00244 **************************************************************/ 00245 /*** Extern ***/ 00246 00247 /*** Globals ***/ 00248 00249 /*** Static Globals ***/ 00250 00251 /* 00252 ************************************************************** 00253 * Function Prototypes 00254 **************************************************************/ 00255 /* 00256 ****************************************************************************** 00257 * 00258 * Function: u8fnADCConvert() 00259 * 00260 */ 00272 uint8_t u8fnADCConvert(const uint8_t cu8ADCInstance, 00273 const uint8_t cu8ADCCh, 00274 uint16_t* pu16Result); 00275 /* 00276 ****************************************************************************** 00277 * 00278 * Function: u8fnADCConfig() 00279 * 00280 */ 00290 uint8_t u8fnADCConfig(uint8_t u8Instance, ADCConfig_t* ptADCConfig); 00291 /* 00292 ****************************************************************************** 00293 * 00294 * Function: u8fnADCSelectRegIndex() 00295 * 00296 */ 00307 static uint8_t u8fnADCSelectRegIndex(uint8_t u8Channel, uint16_t* pu16Mask); 00308 /* 00309 ****************************************************************************** 00310 * 00311 * Function: u8fnADCChannelConfig() 00312 * 00313 */ 00324 uint8_t u8fnADCChannelConfig(const ADCChConfig_t* tADCChConfig, 00325 const uint16_t* pu16Results); 00326 /* 00327 ****************************************************************************** 00328 * 00329 * Function: u8fnADCReadChannel() 00330 * 00331 */ 00342 uint8_t u8fnADCReadChannel(uint8_t u8Instance, 00343 uint8_t u8Channel, 00344 uint16_t* pu16ADCResult); 00345 /* 00346 ****************************************************************************** 00347 * 00348 * Function: u8fnADCStatus() 00349 * 00350 */ 00359 uint8_t u8fnADCStatus(uint8_t u8Instance); 00360 /* 00361 ****************************************************************************** 00362 * 00363 * Function: u8fnADCNormalConversionEnable() 00364 * 00365 */ 00374 uint8_t u8fnADCNormalConversionEnable(uint8_t u8Instance, uint8_t u8Enable); 00375 /* 00376 ****************************************************************************** 00377 * 00378 * Function: vfnADCEoCIsr() 00379 * 00380 */ 00387 static void vfnADCEoCIsr(uint8_t u8Instance); 00388 /* 00389 ****************************************************************************** 00390 * 00391 * Function: vfnADC0EoCIsr() 00392 * 00393 */ 00401 void vfnADC0EoCIsr(void); 00402 /* 00403 ****************************************************************************** 00404 * 00405 * Function: vfnADC1EoCIsr() 00406 * 00407 */ 00415 void vfnADC1EoCIsr(void); 00416 /* 00417 ****************************************************************************** 00418 * 00419 * Function: vfnADC1ErrIsr() 00420 * 00421 */ 00428 static void vfnADCErrIsr(uint8_t u8Instance); 00429 /* 00430 ****************************************************************************** 00431 * 00432 * Function: vfnADC0ErrIsr() 00433 * 00434 */ 00442 void vfnADC0ErrIsr(void); 00443 /* 00444 ****************************************************************************** 00445 * 00446 * Function: vfnADC1ErrIsr() 00447 * 00448 */ 00456 void vfnADC1ErrIsr(void); 00457 /* 00458 ****************************************************************************** 00459 * 00460 * Function: vfnADCWatchDogIsr() 00461 * 00462 */ 00469 static void vfnADCWatchDogIsr(uint8_t u8Instance); 00470 /* 00471 ****************************************************************************** 00472 * 00473 * Function: vfnADC0WatchDogIsr() 00474 * 00475 */ 00483 void vfnADC0WatchDogIsr(void); 00484 /* 00485 ****************************************************************************** 00486 * 00487 * Function: vfnADC0WatchDogIsr() 00488 * 00489 */ 00497 void vfnADC1WatchDogIsr(void); 00498 00499 #endif /* _FILENAME_H */